1. Field of the Invention
This invention relates generally to cascode amplifiers, and more particularly to a cascode amplifier that controls gain by switching signal current to different nodes in a loading network.
2. Description of the Related Art
Cascode amplifiers are commonly used as low noise amplifiers (LNAs) because they provide high output resistance, good voltage gain, and improved reverse isolation over a single transistor amplifier. FIG. 1 is a schematic diagram of a basic cascode amplifier implemented with bipolar junction transistors (BJTs). The circuit of FIG. 1 includes a first transistor Q1 arranged in a common emitter configuration, and a second transistor Q2 arranged in a common base (also referred to herein as a cascode) configuration. The basic cascode amplifier can also be implemented with metal oxide semiconductor (MOS) transistors, in which case the first transistor is arranged in a common source configuration, and the cascode transistor is arranged in a common gate configuration.
To provide electronic gain control, a second cascode transistor can be used to divert signal current from the first cascode transistor, thereby changing the gain of the amplifier. This technique is sometimes referred to as either a "bypass" technique, because the signal current flowing through the second cascode transistor bypasses the first cascode transistor, or as a "current robbing" technique because the second cascode transistor "steals" signal current from the first.
FIG. 2 is a schematic diagram of a prior art variable-gain cascode amplifier that utilizes the bypass technique. This circuit is described thoroughly in "Introduction to RF Frequency Design," Wes Hayward, 1994, American Radio Relay League, Inc., pp. 249-52, but for convenience, is summarized here.
Referring to FIG. 2, the AC input signal is applied to the base of transistor Q1 through capacitor C1, and the output signal is taken from the collector of transistor Q3 through capacitor C2. FIG. 3 is an equivalent circuit showing the small-signal model of the circuit of FIG. 2. Resistors R3, R4, Re, and R2 establish the DC bias current in Q1. The maximum gain of the amplifier is achieved when Vcontrol is pulled low relative to the bias voltage on the base of Q3. When Q2 is off, all of the current through Q1 (both DC bias current and AC signal current) flows through Q3. The gain at maximum gain is determined by Rc, Re, and the g.sub.m of Q1. Resistors R1 and R2 do not affect the AC gain (except to the extent that R2 determines the bias current, and thus the transconductance and emitter resistance of Q1-Q3) because capacitors C3 and C4 provide AC grounds which effectively eliminate resistors R1 and R2 from the small-signal model as shown in FIG. 3. In other words, resistors R1 and R2 carry DC bias current but not AC signal current.
When Vcontrol is pulled high, Q2 begins to turn on and divert some of the current from Q3, thereby reducing the gain of the amplifier. As the voltage of the control signal Vcontrol keeps increasing, more current from the collector of Q1 is diverted from Q3 to Q2 further reducing the gain.
A disadvantage of the circuit of FIG. 2 is that it is not readily adaptable to providing a fixed gain step between a high gain level and a low gain level. This is because the strong hyperbolic tangent function of the differential pair formed by Q2 and Q3 causes very large changes in output current in response to small changes in Vcontrol. To provide accurate gain switching between two gain levels, Vcontrol would have to be controlled with extreme accuracy. Thus, the circuit of FIG. 2 is inherently difficult to adapt to applications that require a fixed gain step since all signal current is either presented to the output, or shunted to an AC ground via C3.
Another disadvantage of the circuit of FIG. 2 is that if Q2 is driven on to the extent that Q3 switches off, then no drive signal remains at the output (as is apparent from the small signal model of FIG. 3), and the amplifier has essentially no gain at all (except for leakage). Thus, if Q2 and Q3 are operated as a pair of switches (which is realatively easy to accomplish due to the strong nonlinearity of the hyperbolic tangent function), the amplifier only provides a step between a finite gain and no gain, rather than a step between a high gain and a low gain.
FIG. 4 is a schematic diagram of another prior art cascode amplifier with electronic gain control which also uses a type of bypass technique. This circuit was described at the course "RF IC Design for Wireless Communication Systems" by Josef Fenk, Jul. 3-7, 1995, at Ecole Polytechniquie Federale De Lausanne, Lausanne, Switzerland, page 28 of handout.
Referring to FIG. 4, the AC input signal is applied to the base of transistors Q10 and Q11, and the AC output signal is taken from the collector of transistors Q13 and Q14. When the gain control terminal is pulled to ground, all of the AC signal passes through Q13 and Q14 to the output terminal, and the amplifier operates in high gain mode.
When the gain control signal is pulled to VCC, the portion of the AC signal current flowing through Q13 is diverted to the power supply (an AC ground) through Q12, and only that portion of the signal current flowing through Q14 is available at the output terminal. Thus, the amplifier operates in low gain mode when Q12 is on. By choosing the appropriate emitter area ratios between Q12/Q13 and Q10/Q11, one can get accurately controlled gain switching at the output. For example, if Q11 and Q13 have nine times the emitter area of Q10 and Q12, one will get a 10:1 change in current at the RF output. For a given load, this results in a 20 dB gain change.
FIG. 5 is a schematic diagram of an implementation of the cascode amplifier of FIG. 4 in which transistor Q11 is implemented as nine transistors Q11A to Q11I. To preserve accuracy, transistor Q13 is implemented as nine transistors Q13A to Q13I. If the emitter area of all of the transistors are equal, then the signal current available at the output terminal in low gain mode is one-tenth that available in high gain mode.
The circuit of FIG. 4 provides an accurately controlled fixed gain step in response to a digital gain control signal, and thus, is better suited to switched-gain LNA RF applications than the circuit of FIG. 2. However, the circuit of FIG. 4 also has several disadvantages. First, because transistors Q11 and Q13 must be implemented as either a plurality of transistors or with emitter areas that are significantly larger than transistors Q10 and Q12, they take up extra chip area when the circuit is fabricated on an integrated circuit.
A further problem with the circuit of FIG. 4 is that the bypassed signal current is returned to the power supply and is therefore wasted. Also, since the signal current is returned to the power supply, isolation becomes a problem because the signal current can get back to the RF output via the bias circuitry. Although the isolation problem can be alliviated by returning the bypassed signal current to a separate power supply, this requires the use of an additional pin when the circuit is fabricated on an integrated circuit.
A futher problem with the circuit of FIG. 4 is the large parasitic capacitance associated with transistors Q11 and Q13.
Finally, since the ratio of non-diverted signal current in high and low gain mode is determined by the emitter area ratios of the transistors, the gain step is fixed and the user cannot adjust it externally.
Accordingly, a need remains for a switched-gain cascode amplifier that overcomes the disadvantages described above.